How to highlight VHDL code blocks in Typst?

Questions
1

Minimal Working Example:

```vhdl 
library ieee;
use ieee.std_logic_1164.all
\```

Remove the \ from the code above (I couldn’t write the last line without it).

It seems there’s no implementation of highlighting VHDL code in Typst, how can I do something to add this functionality?

Thanks.

2

@Andrew’s answer here gives a good breakdown of adding syntax highlighting:

The “hard part” is finding or creating a sublime-syntax file for VHDL.

Related questions:

2 Likes
3

To elaborate on @gezepi’s answer specifically for VHDL:

Typst currently uses the definitions from the two-face crate which inherits definitions from bat. The VHDL language was recently added in bat but two-face is still using an older bat version. I guess eventually the VHDL syntax will trickle down to Typst. In the meantime you can manually copy the syntax file from here to your project directory and do something like this:

#show raw.where(lang: "vhdl"): set raw(syntaxes: "VHDL.sublime-syntax")

```vhdl
library ieee;
use ieee.std_logic_1164.all
```

(Hint: to show here a code block including triple backticks, you can wrap it in quadruple backticks.)

Edit: related Typst issues: raw syntax-highlighting definitions are out of date · Issue #6850 · typst/typst · GitHub and Add syntax highlighting for Svelte 5 · Issue #4419 · typst/typst · GitHub .

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5

That’s the solution, thanks.